FIGS. 1 through 5 illustrate various aspects of a known FET package, wherein the power FETs are eutectically attached directly to the base of the package. In high power microwave applications, direct attachment of the power FETs to the package base is favored so that the greatest possible heat sinking can be achieved.
As shown in FIGS. 1 through 3, package 10 is fabricated from many separate parts, including package base 11 with raised FET mounting pedestal 12, package side walls 15 with lead out assembly 14 and leads 13.
As shown particularly in FIGS. 2 and 3, package side walls 15 are supported by rectangular shim 16. Lead out assembly 14, as shown in FIG. 4, has an upper component, a lower component, both formed from an alumina ceramic, and a conductive trace. The printed metallization conductive trace couples circuitry within the package to external circuitry.
As shown in FIG. 5, FET dies 17 are eutectically attached to the top surface of mounting pedestal 12. Each FET die contains a plurality of individual FETs, which are coupled together. Eutectic attachment defines a process wherein an alloy with a low melting temperature, typically gold based, is used to form a thermally and electrically conductive bond between a metallized back surface of the FET dies and a mounting surface. The liquidus temperature of the alloy increases each time it is remelted, as its chemical composition changes.
Not illustrated in FIGS. 1 through 5 are the many individual shims and spacers needed to bring the electrical circuits and components into proper alignment with one another. In most known FET packages, the top surfaces of all the individual components are roughly coplanar.
This type of known package has many shortcomings. Most obviously it is fabricated from many small, discrete components, each of which must be separately manufactured, placed, and secured to complete the package. This increases the cost of the finished package.
Lead out assembly 14's conductive trace is only a very thin metal film. As such, the amount of current it can carry is limited.
The mounting of FET dies 17 on mounting pedestal 12 is a source of several problems. As the FET dies are mounted on pedestal 12 after side walls 15 are already in place, the assembler placing the FET dies on the pedestal has only restricted access to the work area. The FET die is placed on the pedestal and sufficient heat is applied to the pedestal to eutectically bond the die to the pedestal using a eutectic preform. Typically this requires that the assembler move the die back and forth on the pedestal as the gold alloy used to form the eutectic bond becomes molten. This action is known as "scrubbing". As additional dies are placed on the pedestal, the pedestal must remain heated as the new die are scrubbed across the pedestal. As more dies are placed on the pedestal, less and less space remains for scrubbing.
Given that typical high power FET packages contain from 2 to 4 FET dies, those dies that are placed first on the pedestal experience repeated or extended high temperature as each additional die is placed on the pedestal. This repeated or extended thermal stress can by itself lead to the degradation or failure of FET dies.
If the scrubbing process is not done properly, micro-voids form between the FET die and the pedestal. Unless these are detected using X-ray radiographic examination and eliminated during rework, the long term reliability of the FET die may be sacrificed. The bond to the pedestal provides a critical heat sink path for the FET die. The presence of a microvoid results in uneven thermal conductivity across the die/pedestal interface and gives rise to hot spots on the FET die surface. These hot spots can lead to early failure. Unfortunately, if there is insufficient room on the pedestal to permit adequate scrubbing, the chance of these micro-voids occurring is increased.
Even if the micro-voids are detected before power is applied to the device, attempts to rework the die/pedestal connection apply even more thermal stress to the other FET dies on the pedestal, as the rework temperature is higher than the original eutectic temperature, without any guarantee that the connection can be successfully reworked. The percentage of successfully reworked packages is typically between 20-50%. All FET dies and often the package from an unsuccessfully reworked assembly must be scrapped.
The numerous parts required to form a completed FET package, the high thermal stress placed on the components during assembly, and the large amount of assembly time and effort needed to assemble the FET package all result in a very low yield product having a high manufacturing cost.